1. Field of Invention
The present invention relates to the field of semiconductor devices, including the production of metal oxide semiconductor (MOS) devices. More particularly, the present invention relates to power semiconductor devices made using processes to create field effect transistor (FET) devices with optimized channel-length-to-area ratios, commonly referred to as aspect ratios. More particular yet, the present invention relates to the optimization of device layout methodology based on a mathematical construct known as fractional dimension analysis, or fractal analysis, to achieve high aspect ratios.
2. Description of Prior Art
Applications in which power semiconductor MOS field effect transistors (MOSFETs) using double-diffusion MOS (DMOS) process technology are found range from high-voltage telecommunications circuits down to 3.3 volt DC-DC converters used on personal computers. A power MOSFET is essentially a large array of unit-cell DMOS transistors with several additional elements designed to evenly distribute gating signals and to control device breakdown voltage. The resulting grouping of individual transistors on a single die reduces total ON-state resistance, or ON-resistance, when the power MOSFET is active. Lower ON-resistances yield DMOS devices having lower power dissipation and higher speed charge movement. Accordingly, DMOS technology is preferred in high voltage circuitry of today's high-power integrated circuit applications.
The structural relationships within the power MOS devices are directly related to the ultimate ON-state resistance of a given circuit. In that regard, each transistor of a grouping in a power semiconductor device has an electrical behavior that is directly proportional to its aspect ratio. The aspect ratio is defined by the relationship between a transistor's channel width (W) and its area. Hence, the aspect ratio for a given transistor topology will be a strong function of the shape chosen to implement device geometry. The aspect ratio is a function of the shape of the transistor's active area and is generally defined as the channel perimeter divided by the channel area. For example, a common power MOSFET configuration includes a hexagonally-shaped active area, as illustrated in FIG. 1. For that shape, the aspect ratio (AR) is calculated from equation (1): EQU AR=4*h/(s+h).sup.2 Equation (1)
Of course, it is easy to see that aspect ratio values can be calculated for other unit cell shapes (i.e., squares, circles, etc.).
Maximizing aspect ratios of transistors results in an important lowering of the transistor's channel resistance, thereby contributing to a desired reduction in total transistor ON-resistance. Correspondingly, placing resistive regions of a channel in parallel so as to lower the channel's effective resistance reduces the channel resistance. Increases in this "channel paralleling" also lead to increases in transistor aspect ratios. Typically, aspect ratios for closed-cell geometries, such as the hexagon of FIG. 1, are less than one under the most advanced of existing semiconductor fabrication methods. That can easily be seen in the case where the dimensions h and s shown in FIG. 1 are equal to 1.0 .mu.m, something that is currently not achievable for mass production power devices. If that were possible, an aspect ratio of 1 would be developed. Instead, existing fabrication methods yield transistors with aspect ratios of only about 0.3. Thus, it would be of considerable advantage in reducing ON-resistance to be able to fabricate transistors with aspect ratios of 1 or greater. In addition to faster operation and lower power drain, transistors with optimized aspect ratios provide for efficient silicon utilization.
Concurrent with the development of the field of power MOS device fabrication, there have been developments in the analysis of topographic and profile data. Some of this development has included fractional dimension analysis, or fractal analysis. Fractal analysis is borne out of the mathematical study of fractals. A fractal is a geometric shape that is complex and equally detailed in structure at any level of magnification--i.e., fractals are typically "self-similar" meaning that they have the property that each small portion of the fractal can be viewed as a reduced-scale replica of the whole. One such example of a fractal is the "Koch Curve" as shown in FIGS. 2a-2c. The Koch Curve is named after mathematician Helge Von Koch who introduced this technique in 1904.
The Koch Curve is a classic illustration of fractal development where systematic changes to a given shape are iterated to form a fractal. Such changes could be either additions to the whole or subtractions from the whole, but more importantly the changes are patterned replications. In FIG. 2a, a straight line of unit length is divisible into three equal lengths. The middle length is replaced with an equilateral triangle in FIG. 2b. This change to the whole is then replicated in FIG. 2c to result in a simple fractal. Mathematically, it should be noted that the straight line of FIG. 2a increases in length by four-thirds in FIG. 2b and increases in length again by four-thirds in FIG. 2c, or an increase of sixteen-ninths from the original straight line in FIG. 2a. Although the Koch Curve is only taken to two iterations, it becomes clear that even an initial straight line could develop into a very complex figure through multiple iterations.
An important occurrence in the study of fractals was the development of fractal geometry by the mathematician Benoit B. Mandelbrot. Fractal geometry redefined the concept of "dimension" with respect to Euclidean geometry. In fractal geometry, the dimension of a fractal must be used as an exponent when measuring its size. This means that a fractal cannot be treated as existing strictly in one, two, or any other whole-number dimension. Instead, it must be handled mathematically as though it has some fractional dimension. Theoretical in derivation, true fractal geometries are an idealization. No curve or surface in the real world is a true fractal. However, theoretical fractal geometries may be approximated in physical objects.
One prior-art method using fractal analysis in this manner to quantify the topographic structure of a surface is taught by Brown et al. (U.S. Pat. No. 5,307,292). The method of Brown et al. is a fractal-based analysis of a given structure's topography. His method simulates covering the surface of the structure with triangular patches in order to determine the relative surface area that is a function of patch size or scale of observation. The total measured area value is divided by the projected area value to obtain a relative area value. The relative values for several patch area values are plotted to obtain a slope and a threshold point. The threshold point is indicative of a point which separates the relatively large scales of observation or interaction which are best described by Euclidean geometry from those smaller ones which are best described by fractal geometry. Although the analytical method of Brown et al. appears useful in design, analysis, and manufacture of surfaces where sub-micron technologies are critical (e.g., adhesion, wear, friction, lubrication, corrosion, . . . etc.), this method is limited to just such topographical concerns.
In more relevant context, fractals may be seen to be applicable in a transistor fabrication setting for the following reason. Fractals are basically fragmented geometric shapes that can be subdivided into well-defined sub-shapes coming from the primary geometry. The advantage in this characteristic is that consistent optimization of the aspect ratio becomes possible for a given fabrication process technology. The advantage of using fractal analysis in the semiconductor field is only now being realized, as is evident from a paper written by Samavati et al. entitled "Fractal Capacitors," 1998 IEEE International Solid-State Circuits Conference, Digest of Papers. In that paper, Samavati describes the possibility of fabricating a fractal capacitor taking advantage of, in theory, infinite periphery dimensions in a finite area to significantly increase capacitance in a fixed area. While the Samavati reference explores only MOS capacitors, it provides a strong foundation to augment the current MOSFET technology. MOS devices form a critical part of power device design, and in particular, the efforts to optimize aspect ratios are related, to an extent, to that disclosed by Samavati. However, that reference is limited to the description of a relatively simple passive semiconductor device. It fails to account for the considerable processing requirements associated with active semiconductor devices, such as power MOSFETs.
Accordingly, the prior art fails to provide any structural solution (e.g., hexagonal shaping) or analytical solution (e.g., the method of Brown et al.) to increasing aspect ratios of sub-surface structures adequately for today's applications--in particular for power MOS devices. Therefore, what is needed is a fabrication process that provides unique power MOS devices with aspect ratios exceeding those available through current processing techniques. What is also needed is such a method and resultant power MOS structure that ensures an increased junction perimeter while maintaining active cell area. Further, what is needed is such a method that utilizes fractal theory to provides geometric values easily incorporated into current photolithographic fabrication of power MOS devices.